In many fields, increasing use is being made of clock-timed systems for energy balance reasons. This applies in particular to the motor vehicle field, and, in that context, especially for the operation of inductive loads. In many fields it is also essential or at least advantageous to monitor these clock-timed systems while they are operating. A great variety of corresponding monitoring systems and circuit arrangements for monitoring are known.
U. Tietze and Ch. Schenk: "Halbleiter-Schaltungstechnik" (Semiconductor circuit technology), Springer-Verlag, Berlin, Heidelberg, N.Y., describes numerous basic electronic circuits. Reference is made at this juncture to the chapter "Schaltwerke (Sequentielle Logik)" (Switching mechanisms (sequential logic)) on pages 232 ff. of the 10th edition of the aforementioned book. On page 234 f., a D-flip-flop is described as an example of a basic circuit.
Braking systems implemented in motor vehicles may be clock-timed systems in which the circuit arrangement according to the present invention can be used, for example. German Patent Application No. 195 46 682 describes a hydraulic braking system for performing a driver-independent and wheel-selective braking action. German Patent Application No. 195 29 363 describes a hydraulic braking system of an ABSR system.
It is of course also possible to use the circuit arrangement according to the present invention in a pneumatic braking system.
What is problematic in terms of monitoring of a clock-timed load is that a load signal used for monitoring is also present as a clock-timed signal. In conventional arrangements, the clock-timed load signal that is to be monitored is connected to an input of a microcomputer or microcontroller. At each active clock phase, the microcomputer checks whether the clock-timed load signal to be monitored conforms to the required value.
A disadvantage of the conventional arrangements is that correspondingly fast inputs of the microcomputer must be made available for monitoring the clock-timed load signal. During each active clock phase (which in some cases can be very short), the microcomputer must check whether the clock-timed load signal that is present conforms to a given value. This requires a high level of circuit engineering complexity. Monitoring systems of this kind are correspondingly complex and cost-intensive to implement. A further disadvantage is that monitoring arrangements of this kind have high power consumption due to the high processing speed required.